[RISCV] Remove unneeded AddedComplexity from Xqcibi patterns. NFCI #148301
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We don't have any tests that show why this AddedComplexity is needed. ImmLeafs are automatically ranked higher than register operands so there is no ambgiuity with the base ISA here. If there's some reason I'm missing, please explain and I'll add a comment.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesWe don't have any tests that show why this AddedComplexity is needed. ImmLeafs are automatically ranked higher than register operands so there is no ambgiuity with the base ISA here. If there's some reason I'm missing, please explain and I'll add a comment. Full diff: https://github.com/llvm/llvm-project/pull/148301.diff 1 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 9e3eb1c03fb37..286d44a9c1f72 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1417,7 +1417,7 @@ def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
/// Branches
-let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2 in {
+let Predicates = [HasVendorXqcibi, IsRV32] in {
def : BcciPat<SETEQ, QC_BEQI, simm5nonzero>;
def : BcciPat<SETNE, QC_BNEI, simm5nonzero>;
def : BcciPat<SETLT, QC_BLTI, simm5nonzero>;
@@ -1445,7 +1445,7 @@ def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>
def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
-} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
+} // let Predicates = [HasVendorXqcibi, IsRV32]
let Predicates = [HasVendorXqcibm, IsRV32] in {
def : Pat<(sext_inreg (i32 GPR:$rs1), i1), (QC_EXT GPR:$rs1, 1, 0)>;
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svs-quic
approved these changes
Jul 12, 2025
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I am unable to recollect why I added this. Given that the tests are passing I think we can land this.
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We don't have any tests that show why this AddedComplexity is needed. ImmLeafs are automatically ranked higher than register operands so there is no ambgiuity with the base ISA here. If there's some reason I'm missing, please explain and I'll add a comment.